Semiconductor assemblies with multi-level substrates and associated methods of manufacturing

ABSTRACT

Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. In one embodiment, a substrate for carrying a semiconductor die includes a first routing level, a second routing level, and a conductive via between the first and second routing levels. The conductive via has a first end proximate the first routing level and a second end proximate the second routing level. The first routing level includes a terminal and a first trace between the terminal and the first end of the conductive via. The second routing level includes a second trace between the second end of the conductive via and a ball site. The terminal of the first routing level and the ball site of the second routing level are both accessible for electrical connections from the same side of the substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. application Ser. No. 13/206,321filed Aug. 9, 2011, now U.S. Pat. No. 8,637,987, which is incorporatedherein by reference.

TECHNICAL FIELD

The present disclosure is related to semiconductor assemblies withmulti-level substrates and associated methods of manufacturing.

BACKGROUND

Board-on-chip (“BOC”) techniques have been used for packaging high speedmemory components. FIG. 1A is a cross-sectional view of a BOCsemiconductor assembly in accordance with the prior art. As shown inFIG. 1A, the semiconductor assembly 100 includes a substrate 102, asemiconductor die 104 attached to the substrate 102 with an adhesive106, and an encapsulant 108 encapsulating the semiconductor die 104 andat least a portion of the substrate 102. The substrate 102 includes afirst side 102 a proximate the semiconductor die 104, a second side 102b opposite the first side 102 a, and an opening 118 between the firstand second sides 102 a and 102 b. The opening 118 exposes a connectionregion 110 on the semiconductor die 104. A plurality of traces 112 arelocated on the second side 102 b of the substrate 102 and areelectrically connected to the connection region 110 via a plurality ofwirebonds 114. A plurality of electrical couplers 116 (e.g., solderballs) are attached to ball sites on the substrate 102.

FIG. 1B is a bottom view of the semiconductor assembly 100 of FIG. 1A,and FIG. 1C is an enlarged view of a portion of the semiconductorassembly 100 shown in FIG. 1B. As shown in FIGS. 1B and 1C, thesemiconductor die 104 can include a plurality of bond sites 119 in theconnection region 110. The individual bond sites 119 are coupled tocorresponding terminals 113 of the individual traces 112 on thesemiconductor substrate 102 via the wirebonds 114. As is clearly shownin FIGS. 1B and 1C, the plurality of traces 112 fan out from theterminals 113 to contact corresponding ball pads 120.

Over the course of time, manufacturers have made dies smaller andsmaller to meet user demands. As the semiconductor dies 104 have becomesmaller, the number of ball pads 120 and the traces 112 required on thesubstrate 102 has increased such that the large ball pads 120 caninterfere with routes of the traces 112. One conventional solution fordealing with this problem is to use aggressive design rules and wirebond profiles to decrease the sizes of all features on both thesemiconductor die 102 and the substrate 104. However, such aconventional technique is still limited due to the number of ball pads120 that are typically required.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates a BOC semiconductor assembly in accordance with theprior art.

FIG. 1B is a bottom view of the BOC semiconductor assembly of FIG. 1A.

FIG. 1C is an enlarged view of the BOC shown in FIG. 1B.

FIG. 2A illustrates a BOC semiconductor assembly with a multi-levelsubstrate in accordance with embodiments of the present technology.

FIGS. 2B and 2C are plan views of first and second substrate levels,respectively, of the multi-level substrate shown in FIG. 2A.

FIGS. 3A and 3B illustrate a process of forming the multi-levelsubstrate shown in FIG. 2A, in accordance with embodiments of thetechnology.

FIG. 4A illustrates a BOC semiconductor assembly with a multi-levelsubstrate in accordance with additional embodiments of the presenttechnology.

FIGS. 4B and 4C are plan views of first and second substrate levels ofthe multi-level substrate shown in FIG. 4A.

FIGS. 5 and 6 illustrate BOC semiconductor assemblies with a multi-levelsubstrate in accordance with further embodiments of the presenttechnology.

DETAILED DESCRIPTION

Various embodiments of semiconductor assemblies with multi-levelsubstrates and associated methods of manufacturing are described below.Typical semiconductor assemblies or packages include microelectroniccircuits or components, thin-film recording heads, data storageelements, microfluidic devices, and other components manufactured onmicroelectronic substrates. Substrates can include semiconductor pieces(e.g., doped silicon wafers or gallium arsenide wafers), non-conductivepieces (e.g., various ceramic substrates), or conductive pieces. Aperson skilled in the relevant art will also understand that thetechnology may have additional embodiments, and that the technology maybe practiced without several of the details of the embodiments describedbelow with reference to FIGS. 2A-6.

FIG. 2A illustrates a BOC semiconductor assembly 200 with a multi-levelsubstrate 202 configured in accordance with embodiments of the presenttechnology. As shown in FIG. 2A, the semiconductor assembly 200 caninclude the multi-level substrate 202, a semiconductor die 204 attachedto the substrate 202 with an adhesive 206, and an encapsulant 208encapsulating the semiconductor die 204 and at least a portion of thesubstrate 202. The semiconductor die 204 can include a memory die, aprocessor, and/or other suitable types of dies. The encapsulant 208 caninclude an epoxy and/or other suitable compositions. Even though aparticular arrangement of the foregoing components is shown in FIG. 2Afor illustration purposes, in other embodiments, the semiconductor die204 may also be attached to the substrate 202 in a flip-chipconfiguration and/or other suitable configurations.

In the illustrated embodiment, the substrate 202 can include a firstside 202 a proximate the semiconductor die 204, a second side 202 bopposite the first side 202 a, and an opening 218 extending through thesubstrate 202 from the first side 202 a to the second side 202 b. Theopening 218 exposes a connection region 210 on the semiconductor die204. The connection region includes bond sites 219 that are connectedinternally to structures within the semiconductor die 204. In otherembodiments, the opening 218 may be omitted, for example, if thesemiconductor die 204 is coupled to the substrate 202 in a flip-chipconfiguration.

As shown in FIG. 2A, the substrate 202 includes a first routing level211, a second routing level 212, and conductive vias 213 between thefirst and second routing levels 211 and 212. The individual first andsecond routing levels 211 and 212 can be in generally parallel planes,and can include a trace, a plate, and/or other suitable routingstructures. Individual conductive vias 213 can include a first end 213 ain contact with the first routing level 211 and a second end 213 b incontact with the second routing level 212. In the illustratedembodiment, a plurality of wirebonds 214 electrically connect individualbond sites 219 at the connection area 210 of the semiconductor die 204to the first routing level 211. In other embodiments, at least some ofthe wirebonds 214 can also be connected to the second routing level 212,as described in more detail below with reference to FIG. 4A. In furtherembodiments, the substrate 202 may include three, four, or any othersuitable number of routing levels in configurations generally similar toor different from that shown in FIG. 2A, depending upon the embodiment.In any of these embodiments, the second ends 213 b of the individualvias 213 can be electrically connected to individual ball sites 224 viaconnectors 226. The ball sites 224 can be configured as a ball gridarray to receive a plurality of electrical couplers 216 (e.g., solderballs) as shown in FIG. 2A.

FIGS. 2B and 2C are bottom views of the first and second routing levels211 and 212, respectively. As shown in FIG. 2B, the individual wirebonds214 are electrically coupled between a terminal 215 of the individualtrace 222 on the first routing level 211 and corresponding bond sites219 in the connection region 210. The individual traces 222 fan out fromthe terminals 215 to connect with the first ends 213 a of the conductivevias 213. As shown in FIG. 2C, the second routing level 212 includes thesecond ends 213 b of the individual vias 213, which are electricallyconnected to corresponding ball sites 224 with corresponding connectors226, as discussed above with reference to FIG. 2A. The bond sites 219(FIG. 2B) and the ball sites 224 (FIG. 2A) can be accessible from thesame side (e.g., the same major surface) of the substrate 202, as shownin FIG. 2A. As a result, and with continued reference to FIG. 2A, thewire bonds 214 and electrical couplers 216 (e.g., solder balls) canreadily be connected to the substrate 202 from the same side of thesubstrate 202.

As shown in FIGS. 2B and 2C, the first routing level 211 of thesubstrate 202 has a plurality of traces 222 that fan out to form atarget pattern of the first ends 213 a of the conductive vias 213. Theillustrated first routing level 211 does not include any ball sites. Asa result, the traces 222 can fan out without hindrance from the ballsites 224 because the ball sites 224 are on the second routing level 212which is in a different plane than the plane containing the traces 222.In other words, the traces 222 on the first routing level 211 can passunder or over any number of ball sites 224 without interference from theball sites 224 because the ball sites 224 are on the second routinglevel 212. As a result, embodiments of the substrate 202 can accommodatea large number of traces 222 and ball sites 224 even though thesemiconductor die 204 has a small size.

FIGS. 3A and 3B illustrate a process of forming the multi-levelsubstrate 202 in FIG. 2A in accordance with embodiments of thetechnology. As shown in FIG. 3A, the process for forming the firstrouting level 211 and the second routing level 212 are shown side byside for illustration purposes. In certain embodiments these processingstages may be performed concurrently. In other embodiments theseoperating stages may be performed at least partially in series.

As shown in FIG. 3A, separate pieces or elements of a substrate material302 are used to form the first and second routing levels, respectively.The substrate material 302 includes a generally non-conductive core 301with a first conductive material 304 a (e.g. copper) on a first side 301a and a second conductive material 304 b on a second side 301 b. Aninitial stage 310 of forming the first routing level 211 can includestripping the first conductive material 304 a from the first side 301 aof the non-conductive core 301. Subsequently, the second conductivematerial 304 b may be patterned and selectively removed from the secondside 301 b of the non-conductive core 301, forming the first routinglevel 211.

Preparing the second routing level 202 can include stripping the firstconductive material 304 a from the first side 301 a of a separatenon-conductive core 301 (stage 312) and patterning and selectivelyremoving the second conductive material 304 b to form a targeted patternfor the second routing level 212 (stage 314). As shown in FIG. 3A, asolder mask 306 is formed over the second routing level 212 at stage316. In other embodiments the solder mask 306 may be omitted. Stage 316can include removing a portion of the solder mask 306 and the generallynon-conductive core 301 to form a portion of the opening 218 in thesubstrate 202. The formed first and second routing levels 211 and 212can then be generally aligned at stage 318.

As shown in FIG. 3B, the first routing level 211 and the second routinglevel 212 can be laminated together at stage 320. Conductive vias 313between the first and second routing levels 211 and 212 can besubsequently formed at stage 322 using through-substrate via formingtechniques and/or other suitable techniques. Subsequently, thenon-conductive core 301 of the first routing level 211 can beselectively removed to form another portion of the opening 218 in thesubstrate 202 at stage 324. Subsequently, the semiconductor die 204(FIG. 2A) can be attached to the substrate 202 and subsequentlyencapsulated with encapsulant 218 according to conventional techniquesfor BOC packaging.

Even though the wirebonds 214 are shown in FIG. 2A as extending betweenthe connection region 210 of the semiconductor die 204 and the firstrouting level 211, in other embodiments the second routing level 212 canalso include contact areas electrically coupled to the connection region210 of the semiconductor die 204. For example, as shown in FIG. 4A, thesecond routing level 212 can include at least one contact area 230electrically coupled to the connection region 210 of the semiconductordie 204 via a wirebond 215.

As shown in FIG. 4B, the first routing level 211 is shown divided into afirst signal plane 232 and a second signal plane 234 in a side-by-sidearrangement. The individual first and second signal planes 232 and 234are electrically coupled to the connection region 210 with the wirebonds214. In certain embodiments, at least one of the first and second signalplanes 232, 234 can include a power plane, a ground plane, and/or othersuitable signal planes that are electrically common to multipleterminals of the die 204 (FIG. 4A). As shown in FIG. 4C, the secondrouting level 212 can include a plurality of traces 236 that fan outfrom a plurality of terminals 235 into a plurality of ball sites 224.The individual terminals 235 are electrically connected to theconnection region 210 via the wirebonds 215. The first and secondrouting levels 211 and 212 are connected with the conductive vias 213,in a manner generally similar to that discussed above with reference toFIGS. 2A-2C.

FIGS. 5 and 6 are cross-sectional views of BOC semiconductor assemblies500 and 600, respectively, configured in accordance with additionalembodiments of the present technology. Embodiments of the semiconductorassemblies 500 and 600 can be generally similar to those shown in FIGS.2A and 4A, respectively, except that the semiconductor assemblies 500and 600 individually include a conductive material 240 between thesubstrate 202 and the semiconductor die 204. The conductive material 240can include a metal plate, a metal alloy plate, and/or other suitablematerials and/or structures with sufficient thermal conductivity toconduct heat from the semiconductor die 202. In further embodiments, theconductive material 240 may be replaced with other suitable heatconducting components (e.g., Peltier elements) or may be omitted.

One feature of several of the foregoing embodiments is that the tracesand the ball sites to which they connect can be located on differentlevels or strata of the substrate. This arrangement allows the designergreater flexibility when selecting the routes for the traces and thelocations for the ball sites because the routes can follow paths thatare independent of the ball site locations, so long as individual routescan be connected to the corresponding ball sites with vias, as describedabove. Another feature of at least some embodiments is that the ballsites on one level of the substrate and portions of the traces onanother level of the substrate are both accessible from the same side orface of the substrate. This arrangement allows the manufacturer toaccess the traces for wirebonding and access the ball sites fordepositing solder balls or other electrical couplers with the substratefacing the same direction.

From the foregoing, it will be appreciated that specific embodiments ofthe technology have been described herein for purposes of illustration,but that various modifications may be made without deviating from thetechnology. For example, in an embodiment shown in FIG. 3A, the tworouting levels are initially formed on separate non-conductive cores,which are then joined. As part of this process, the conductive materialon one side of each core is removed. In other embodiments, portions ofthis conductive material can remain, e.g., to carry out additionalrouting functions. The traces and ball pads can have arrangementsdifferent than those specifically illustrated in the foregoing Figures.The materials described in the context of particular embodiments abovecan have different constituents and/or properties in other embodiments.

Certain aspects of the technology described in the context of particularembodiments may be combined or eliminated in other embodiments. Further,while advantages associated with certain embodiments of the inventionhave been described in the context of those embodiments, otherembodiments may also exhibit such advantages, and not all embodimentsneed necessarily exhibit such advantages to fall within the scope of theinvention. Accordingly, the disclosure and associated technology canencompass other embodiments not expressly shown or described herein.

I/We claim:
 1. A method of processing a substrate for carrying asemiconductor die, comprising: forming a first routing level; forming asecond routing level; generally aligning the first routing levelrelative to the second routing level; and forming a conductive viabetween the first and second routing levels, the conductive via having afirst end proximate the first routing level and a second end proximatethe second routing level, wherein: the first routing level includes aterminal and a first trace electrically connected between the terminaland the first end of the conductive via; the second routing levelincludes a second trace electrically connected between the second end ofthe conductive via and a ball site; and the terminal and the ball siteare both accessible from the same side of the substrate.
 2. The methodof claim 1 wherein forming the first routing level includes stripping afirst conductive material from a first side of a non-conductive core andpatterning and selectively removing a portion of a second conductivematerial on a second side of the non-conductive core.
 3. The method ofclaim 1 wherein forming the second routing level includes: stripping afirst conductive material from a first side of a non-conductive core andpatterning and selectively removing a portion of a second conductivematerial on a second side of the non-conductive core; and depositing asolder mask on the patterned second conductive material.
 4. The methodof claim 1 wherein forming the second routing level includes: strippinga first conductive material from a first side of a substrate materialand patterning and selectively removing a portion of a second conductivematerial on a second side of the substrate material; depositing a soldermask on the patterned second conductive material; and forming ball padson the second conductive material by selectively removing the depositedsolder mask.
 5. The method of claim 1, further comprising forming anopening through the first and second routing levels after generallyaligning the first routing level to the second routing level.
 6. Themethod of claim 1 wherein forming the first routing level includesforming a first routing level that does not include any ball site. 7.The method of claim 1 wherein forming the first routing level includesforming the first routing level to be carried by a first non-conductivecore, and wherein forming the second routing level includes forming thesecond routing level to be carried by a second non-conductive core, andwherein the method further comprises fixing the first and secondnon-conductive cores relative to each other.
 8. The method of claim 7wherein fixing the first and second non-conductive cores relative toeach other includes bonding the first routing level to a surface of thesecond non-conductive core.
 9. The method of claim 1 wherein forming thefirst routing level includes forming the first routing level on a firstsubstrate, and wherein forming the second routing level includes formingthe second routing level on a second substrate different than the firstsubstrate, and wherein the method further comprises joining the firstand second substrates before forming the conductive via.
 10. The methodof claim 1 wherein the first and second routing levels and theconductive via form a substrate, and wherein the method furthercomprises: mounting a semiconductor die to the substrate; andelectrically connecting the semiconductor die to the first routinglevel.
 11. The method of claim 1 wherein the first and second routinglevels and the conductive via form a substrate, and wherein the methodfurther comprises: forming an opening in the substrate; mounting asemiconductor die to the substrate; and wirebonding the semiconductordie to the terminal of the first routing level first routing level bypassing a bond wire through the opening.